593 lines
18 KiB
ArmAsm
593 lines
18 KiB
ArmAsm
/*
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* FreeRTOS Kernel V11.1.0
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*
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*/
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#include "riscv_encoding.h"
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#ifndef __riscv_32e
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#define portRegNum 30
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#else
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#define portRegNum 14
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#endif
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#define portCONTEXT_SIZE ( portRegNum * REGBYTES )
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#ifdef CONFIG_RISCV_FPU
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#define portCONTEXT_SIZE_FPU ( 20 * REGBYTES )
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#endif
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.section .text.entry
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.align 8
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.extern xPortTaskSwitch
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.extern pxCurrentTCB
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.global prvPortStartFirstTask
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#if CONFIG_FREERTOS_STACK_HW_CHECK
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.extern ulStackTop
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.extern ulStackBottom
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#endif
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/**
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* \brief Global interrupt disabled
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* \details
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* This function disable global interrupt.
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* \remarks
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* - All the interrupt requests will be ignored by CPU.
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*/
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.macro DISABLE_MIE
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csrc CSR_MSTATUS, MSTATUS_MIE
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.endm
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/**
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* \brief Macro for context save
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* \details
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* This macro save ABI defined caller saved registers in the stack.
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* \remarks
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* - This Macro could use to save context when you enter to interrupt
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* or exception
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*/
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/* Save caller registers */
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.macro SAVE_CONTEXT
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csrrw sp, CSR_MSCRATCH, sp
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/* Allocate stack space for context saving */
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#ifndef __riscv_32e
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addi sp, sp, -20*REGBYTES
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#else
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addi sp, sp, -14*REGBYTES
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#endif /* __riscv_32e */
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STORE x1, 0*REGBYTES(sp)
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STORE x4, 1*REGBYTES(sp)
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STORE x5, 2*REGBYTES(sp)
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STORE x6, 3*REGBYTES(sp)
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STORE x7, 4*REGBYTES(sp)
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STORE x10, 5*REGBYTES(sp)
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STORE x11, 6*REGBYTES(sp)
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STORE x12, 7*REGBYTES(sp)
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STORE x13, 8*REGBYTES(sp)
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STORE x14, 9*REGBYTES(sp)
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STORE x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 14*REGBYTES(sp)
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STORE x17, 15*REGBYTES(sp)
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STORE x28, 16*REGBYTES(sp)
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STORE x29, 17*REGBYTES(sp)
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STORE x30, 18*REGBYTES(sp)
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STORE x31, 19*REGBYTES(sp)
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#endif /* __riscv_32e */
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.endm
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/**
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* \brief Macro for restore caller registers
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* \details
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* This macro restore ABI defined caller saved registers from stack.
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* \remarks
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* - You could use this macro to restore context before you want return
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* from interrupt or exeception
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*/
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/* Restore caller registers */
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.macro RESTORE_CONTEXT
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LOAD x1, 0*REGBYTES(sp)
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LOAD x4, 1*REGBYTES(sp)
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LOAD x5, 2*REGBYTES(sp)
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LOAD x6, 3*REGBYTES(sp)
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LOAD x7, 4*REGBYTES(sp)
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LOAD x10, 5*REGBYTES(sp)
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LOAD x11, 6*REGBYTES(sp)
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LOAD x12, 7*REGBYTES(sp)
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LOAD x13, 8*REGBYTES(sp)
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LOAD x14, 9*REGBYTES(sp)
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LOAD x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 14*REGBYTES(sp)
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LOAD x17, 15*REGBYTES(sp)
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LOAD x28, 16*REGBYTES(sp)
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LOAD x29, 17*REGBYTES(sp)
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LOAD x30, 18*REGBYTES(sp)
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LOAD x31, 19*REGBYTES(sp)
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/* De-allocate the stack space */
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addi sp, sp, 20*REGBYTES
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#else
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/* De-allocate the stack space */
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addi sp, sp, 14*REGBYTES
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#endif /* __riscv_32e */
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csrrw sp, CSR_MSCRATCH, sp
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.endm
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/**
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* \brief Macro for save necessary CSRs to stack
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* \details
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* This macro store MCAUSE, MEPC, MSUBM to stack.
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*/
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.macro SAVE_CSR_CONTEXT
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/* Store CSR mcause to stack using pushmcause */
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csrrwi x0, CSR_PUSHMCAUSE, 11
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/* Store CSR mepc to stack using pushmepc */
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csrrwi x0, CSR_PUSHMEPC, 12
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/* Store CSR msub to stack using pushmsub */
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csrrwi x0, CSR_PUSHMSUBM, 13
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.endm
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/**
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* \brief Macro for restore necessary CSRs from stack
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* \details
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* This macro restore MSUBM, MEPC, MCAUSE from stack.
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*/
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.macro RESTORE_CSR_CONTEXT
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LOAD x5, 13*REGBYTES(sp)
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csrw CSR_MSUBM, x5
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LOAD x5, 12*REGBYTES(sp)
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csrw CSR_MEPC, x5
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LOAD x5, 11*REGBYTES(sp)
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csrw CSR_MCAUSE, x5
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.endm
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/**
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* \brief Exception/NMI Entry
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* \details
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* This function provide common entry functions for exception/nmi.
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* \remarks
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* This function provide a default exception/nmi entry.
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* ABI defined caller save register and some CSR registers
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.trap
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/* In CLIC mode, the exeception entry must be 64bytes aligned */
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.align 6
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.global exc_entry
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.type exc_entry, @function
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exc_entry:
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#if CONFIG_FREERTOS_STACK_HW_CHECK
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/* 关闭硬件栈溢出检测 */
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csrw mstack_ctl, 0x0
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#endif
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/* Save the caller saving registers (context) */
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csrrw sp, CSR_MSCRATCH, sp
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/* Allocate stack space for context saving */
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#ifndef __riscv_32e
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/* 让sp进行16字节地址对齐, 否则浮点运行会异常 */
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addi sp, sp, -40*REGBYTES
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#else
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addi sp, sp, -20*REGBYTES
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#endif /* __riscv_32e */
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STORE x0, 0*REGBYTES(sp)
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STORE x1, 1*REGBYTES(sp)
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/* x2/sp寄存器等t0寄存器保存后在保存 */
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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/* 保存t0寄存器 */
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STORE x5, 5*REGBYTES(sp)
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/* 读取之前的SP到t0中 */
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csrr t0, mscratch
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/* 将保存到sp */
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STORE t0, 2*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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csrr t0, mcause
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STORE t0, 32*REGBYTES(sp)
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csrr t0, mepc
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STORE t0, 33*REGBYTES(sp)
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csrr t0, msubm
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STORE t0, 34*REGBYTES(sp)
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#else
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csrr t0, mcause
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STORE t0, 16*REGBYTES(sp)
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csrr t0, mepc
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STORE t0, 17*REGBYTES(sp)
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csrr t0, msubm
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STORE t0, 18*REGBYTES(sp)
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#endif /* __riscv_32e */
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/*
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* Set the exception handler function arguments
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* argument 1: mcause value
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* argument 2: current stack point(SP) value
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*/
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csrr a0, mcause
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mv a1, sp
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/*
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* TODO: Call the exception handler function
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* By default, the function template is provided in
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* system_Device.c, you can adjust it as you want
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*/
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call core_exception_handler
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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mret
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.size exc_entry, . - exc_entry
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/**
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* \brief Non-Vector Interrupt Entry
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* \details
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* This function provide common entry functions for handling
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* non-vector interrupts
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* \remarks
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* This function provide a default non-vector interrupt entry.
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* ABI defined caller save register and some CSR registers need
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.irq
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/* In CLIC mode, the interrupt entry must be 4bytes aligned */
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.align 2
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.global irq_entry
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.type irq_entry, @function
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/* This label will be set to MTVT2 register */
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irq_entry:
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#if CONFIG_FREERTOS_STACK_HW_CHECK
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/* 关闭硬件栈溢出检测 */
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csrw mstack_ctl, 0x0
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#endif
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/* Save the caller saving registers (context) */
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SAVE_CONTEXT
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/* Save the necessary CSR registers */
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SAVE_CSR_CONTEXT
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/* This special CSR read/write operation, which is actually
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* claim the CLIC to find its pending highest ID, if the ID
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* is not 0, then automatically enable the mstatus.MIE, and
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* jump to its vector-entry-label, and update the link register
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*/
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csrrw ra, CSR_JALMNXTI, ra
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/* Critical section with interrupts disabled */
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DISABLE_MIE
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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mret
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.size irq_entry, . - irq_entry
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/* Default Handler for Exceptions / Interrupts */
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.global default_intexc_handler
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.type default_intexc_handler, @function
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default_intexc_handler:
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1:
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j 1b
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.size default_intexc_handler, . - default_intexc_handler
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the stack
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for lazy saving of FPU registers. */
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.section .text
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.type prvPortStartFirstTask, @function
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.align 3
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prvPortStartFirstTask:
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/* Setup Interrupt Stack using
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The stack that was used by main()
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before the scheduler is started is
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no longer required after the scheduler is started.
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Interrupt stack pointer is stored in CSR_MSCRATCH */
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la t0, __StackTop
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csrw CSR_MSCRATCH, t0
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LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
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LOAD sp, 0x0(t0) /* Read sp from first TCB member */
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop mstatus from stack and set it */
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LOAD t0, (portRegNum - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
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LOAD x27, 24 * REGBYTES(sp)
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LOAD x28, 25 * REGBYTES(sp)
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LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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#endif
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addi sp, sp, portCONTEXT_SIZE
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mret
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.size prvPortStartFirstTask, . - prvPortStartFirstTask
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.section .text.irq
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.align 2
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.global eclic_msip_handler
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.type eclic_msip_handler, @function
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eclic_msip_handler:
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#if CONFIG_FREERTOS_STACK_HW_CHECK
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/* 关闭硬件栈溢出检测 */
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csrw mstack_ctl, 0x0
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#endif
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#ifdef CONFIG_RISCV_FPU
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/* Push additional registers */
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addi sp, sp, -portCONTEXT_SIZE_FPU
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FPSTORE ft0, 0 * REGBYTES(sp) /* FT0 */
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FPSTORE ft1, 1 * REGBYTES(sp) /* FT1 */
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FPSTORE ft2, 2 * REGBYTES(sp) /* FT2 */
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FPSTORE ft3, 3 * REGBYTES(sp) /* FT3 */
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FPSTORE ft4, 4 * REGBYTES(sp) /* FT4 */
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FPSTORE ft5, 5 * REGBYTES(sp) /* FT5 */
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FPSTORE ft6, 6 * REGBYTES(sp) /* FT6 */
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FPSTORE ft7, 7 * REGBYTES(sp) /* FT7 */
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FPSTORE fa0, 8 * REGBYTES(sp) /* FA0 */
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FPSTORE fa1, 9 * REGBYTES(sp) /* FA1 */
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FPSTORE fa2, 10 * REGBYTES(sp) /* FA2 */
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FPSTORE fa3, 11 * REGBYTES(sp) /* FA3 */
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FPSTORE fa4, 12 * REGBYTES(sp) /* FA4 */
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FPSTORE fa5, 13 * REGBYTES(sp) /* FA5 */
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FPSTORE fa6, 14 * REGBYTES(sp) /* FA6 */
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FPSTORE fa7, 15 * REGBYTES(sp) /* FA7 */
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FPSTORE ft8, 16 * REGBYTES(sp) /* FT8 */
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FPSTORE ft9, 17 * REGBYTES(sp) /* FT9 */
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FPSTORE ft10, 18 * REGBYTES(sp) /* FT10 */
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FPSTORE ft11, 19 * REGBYTES(sp) /* FT11 */
|
|
#endif
|
|
addi sp, sp, -portCONTEXT_SIZE
|
|
STORE x1, 1 * REGBYTES(sp) /* RA */
|
|
STORE x5, 2 * REGBYTES(sp)
|
|
STORE x6, 3 * REGBYTES(sp)
|
|
STORE x7, 4 * REGBYTES(sp)
|
|
STORE x8, 5 * REGBYTES(sp)
|
|
STORE x9, 6 * REGBYTES(sp)
|
|
STORE x10, 7 * REGBYTES(sp)
|
|
STORE x11, 8 * REGBYTES(sp)
|
|
STORE x12, 9 * REGBYTES(sp)
|
|
STORE x13, 10 * REGBYTES(sp)
|
|
STORE x14, 11 * REGBYTES(sp)
|
|
STORE x15, 12 * REGBYTES(sp)
|
|
#ifndef __riscv_32e
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|
STORE x16, 13 * REGBYTES(sp)
|
|
STORE x17, 14 * REGBYTES(sp)
|
|
STORE x18, 15 * REGBYTES(sp)
|
|
STORE x19, 16 * REGBYTES(sp)
|
|
STORE x20, 17 * REGBYTES(sp)
|
|
STORE x21, 18 * REGBYTES(sp)
|
|
STORE x22, 19 * REGBYTES(sp)
|
|
STORE x23, 20 * REGBYTES(sp)
|
|
STORE x24, 21 * REGBYTES(sp)
|
|
STORE x25, 22 * REGBYTES(sp)
|
|
STORE x26, 23 * REGBYTES(sp)
|
|
STORE x27, 24 * REGBYTES(sp)
|
|
STORE x28, 25 * REGBYTES(sp)
|
|
STORE x29, 26 * REGBYTES(sp)
|
|
STORE x30, 27 * REGBYTES(sp)
|
|
STORE x31, 28 * REGBYTES(sp)
|
|
#endif
|
|
/* Push mstatus to stack */
|
|
csrr t0, CSR_MSTATUS
|
|
STORE t0, (portRegNum - 1) * REGBYTES(sp)
|
|
|
|
/* Push additional registers */
|
|
|
|
/* Store sp to task stack */
|
|
LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
|
STORE sp, 0(t0)
|
|
|
|
csrr t0, CSR_MEPC
|
|
STORE t0, 0(sp)
|
|
jal xPortTaskSwitch
|
|
|
|
/* Switch task context */
|
|
LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
|
LOAD sp, 0x0(t0) /* Read sp from first TCB member */
|
|
#if CONFIG_FREERTOS_STACK_HW_CHECK
|
|
/* 开启硬件栈保护 */
|
|
LOAD t0, ulStackTop
|
|
csrw mstack_base, t0
|
|
LOAD t0, ulStackBottom
|
|
csrw mstack_bound, t0
|
|
csrw mstack_ctl, 0x3
|
|
#endif
|
|
/* Pop PC from stack and set MEPC */
|
|
LOAD t0, 0 * REGBYTES(sp)
|
|
csrw CSR_MEPC, t0
|
|
/* Pop additional registers */
|
|
|
|
/* Pop mstatus from stack and set it */
|
|
LOAD t0, (portRegNum - 1) * REGBYTES(sp)
|
|
csrw CSR_MSTATUS, t0
|
|
/* Interrupt still disable here */
|
|
/* Restore Registers from Stack */
|
|
LOAD x1, 1 * REGBYTES(sp) /* RA */
|
|
LOAD x5, 2 * REGBYTES(sp)
|
|
LOAD x6, 3 * REGBYTES(sp)
|
|
LOAD x7, 4 * REGBYTES(sp)
|
|
LOAD x8, 5 * REGBYTES(sp)
|
|
LOAD x9, 6 * REGBYTES(sp)
|
|
LOAD x10, 7 * REGBYTES(sp)
|
|
LOAD x11, 8 * REGBYTES(sp)
|
|
LOAD x12, 9 * REGBYTES(sp)
|
|
LOAD x13, 10 * REGBYTES(sp)
|
|
LOAD x14, 11 * REGBYTES(sp)
|
|
LOAD x15, 12 * REGBYTES(sp)
|
|
#ifndef __riscv_32e
|
|
LOAD x16, 13 * REGBYTES(sp)
|
|
LOAD x17, 14 * REGBYTES(sp)
|
|
LOAD x18, 15 * REGBYTES(sp)
|
|
LOAD x19, 16 * REGBYTES(sp)
|
|
LOAD x20, 17 * REGBYTES(sp)
|
|
LOAD x21, 18 * REGBYTES(sp)
|
|
LOAD x22, 19 * REGBYTES(sp)
|
|
LOAD x23, 20 * REGBYTES(sp)
|
|
LOAD x24, 21 * REGBYTES(sp)
|
|
LOAD x25, 22 * REGBYTES(sp)
|
|
LOAD x26, 23 * REGBYTES(sp)
|
|
LOAD x27, 24 * REGBYTES(sp)
|
|
LOAD x28, 25 * REGBYTES(sp)
|
|
LOAD x29, 26 * REGBYTES(sp)
|
|
LOAD x30, 27 * REGBYTES(sp)
|
|
LOAD x31, 28 * REGBYTES(sp)
|
|
#endif
|
|
|
|
addi sp, sp, portCONTEXT_SIZE
|
|
#ifdef CONFIG_RISCV_FPU
|
|
/* Pop additional registers */
|
|
FPLOAD ft0, 0 * REGBYTES(sp) /* FT0 */
|
|
FPLOAD ft1, 1 * REGBYTES(sp) /* FT1 */
|
|
FPLOAD ft2, 2 * REGBYTES(sp) /* FT2 */
|
|
FPLOAD ft3, 3 * REGBYTES(sp) /* FT3 */
|
|
FPLOAD ft4, 4 * REGBYTES(sp) /* FT4 */
|
|
FPLOAD ft5, 5 * REGBYTES(sp) /* FT5 */
|
|
FPLOAD ft6, 6 * REGBYTES(sp) /* FT6 */
|
|
FPLOAD ft7, 7 * REGBYTES(sp) /* FT7 */
|
|
FPLOAD fa0, 8 * REGBYTES(sp) /* FA0 */
|
|
FPLOAD fa1, 9 * REGBYTES(sp) /* FA1 */
|
|
FPLOAD fa2, 10 * REGBYTES(sp) /* FA2 */
|
|
FPLOAD fa3, 11 * REGBYTES(sp) /* FA3 */
|
|
FPLOAD fa4, 12 * REGBYTES(sp) /* FA4 */
|
|
FPLOAD fa5, 13 * REGBYTES(sp) /* FA5 */
|
|
FPLOAD fa6, 14 * REGBYTES(sp) /* FA6 */
|
|
FPLOAD fa7, 15 * REGBYTES(sp) /* FA7 */
|
|
FPLOAD ft8, 16 * REGBYTES(sp) /* FT8 */
|
|
FPLOAD ft9, 17 * REGBYTES(sp) /* FT9 */
|
|
FPLOAD ft10, 18 * REGBYTES(sp) /* FT10 */
|
|
FPLOAD ft11, 19 * REGBYTES(sp) /* FT11 */
|
|
|
|
addi sp, sp, portCONTEXT_SIZE_FPU
|
|
#endif
|
|
mret
|
|
.size eclic_msip_handler, . - eclic_msip_handler
|