86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
/*
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* GC2145 register definitions.
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*/
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#ifndef __GC2145_REG_REGS_H__
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#define __GC2145_REG_REGS_H__
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#define CHIP_ID_HIGH 0XF0
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#define CHIP_ID_LOW 0XF1
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#define PLL_MODE1 0XF7
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#define PLL_MODE2 0XF8
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#define CM_MODE 0XF9
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#define CLK_DIV_MODE 0XFA
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#define RESET_RELATED 0xfe // Bit[7]: Software reset
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// Bit[6]: cm reset
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// Bit[5]: mipi reset
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// Bit[4]: CISCTL_restart_n
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// Bit[3]: NA
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// Bit[2:0]: page select
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// 000:page0
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// 001:page1
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// 010:page2
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// 011:page3
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//-page0----------------
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#define P0_EXPOSURE_HIGH 0X03
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#define P0_EXPOSURE_LOW 0X04
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#define P0_HB_HIGH 0X05
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#define P0_HB_LOW 0X06
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#define P0_VB_HIGH 0X07
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#define P0_VB_LOW 0X08
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#define P0_ROW_START_HIGH 0X09
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#define P0_ROW_START_LOW 0X0A
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#define P0_COL_START_HIGH 0X0B
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#define P0_COL_START_LOW 0X0C
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#define P0_WIN_HEIGHT_HIGH 0X0D
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#define P0_WIN_HEIGHT_LOW 0X0E
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#define P0_WIN_WIDTH_HIGH 0X0F
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#define P0_WIN_WIDTH_LOW 0X10
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#define P0_ANALOG_MODE1 0X17
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#define P0_ANALOG_MODE2 0X18
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#define P0_SPECIAL_EFFECT 0X83
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#define P0_OUTPUT_FORMAT 0x84 // Format select
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// Bit[7]:YUV420 row switch
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// Bit[6]:YUV420 col switch
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// Bit[7]:YUV420_legacy
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// Bit[4:0]:output data mode
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// 5’h00 Cb Y Cr Y
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// 5’h01 Cr Y Cb Y
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// 5’h02 Y Cb Y Cr
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// 5’h03 Y Cr Y Cb
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// 5’h04 LSC bypass, C/Y
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// 5’h05 LSC bypass, Y/C
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// 5’h06 RGB 565
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// 5’h0f bypass 10bits
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// 5’h17 switch odd/even column /row to controls output Bayer pattern
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// 00 RGBG
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// 01 RGGB
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// 10 BGGR
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// 11 GBRG
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// 5'h18 DNDD out mode
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// 5'h19 LSC out mode
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// 5;h1b EEINTP out mode
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#define P0_FRAME_START 0X85
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#define P0_SYNC_MODE 0X86
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#define P0_MODULE_GATING 0X88
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#define P0_BYPASS_MODE 0X89
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#define P0_DEBUG_MODE2 0X8C
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#define P0_DEBUG_MODE3 0X8D
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#define P0_CROP_ENABLE 0X90
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#define P0_OUT_WIN_Y1_HIGH 0X91
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#define P0_OUT_WIN_Y1_LOW 0X92
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#define P0_OUT_WIN_X1_HIGH 0X93
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#define P0_OUT_WIN_X1_LOW 0X94
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#define P0_OUT_WIN_HEIGHT_HIGH 0X95
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#define P0_OUT_WIN_HEIGHT_LOW 0X96
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#define P0_OUT_WIN_WIDTH_HIGH 0X97
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#define P0_OUT_WIN_WIDTH_LOW 0X98
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#define P0_SUBSAMPLE 0X99
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#define P0_SUBSAMPLE_MODE 0X9A
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#endif // __GC2145_REG_REGS_H__
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