239 lines
7.9 KiB
C
239 lines
7.9 KiB
C
/*
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* GC032A register definitions.
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*/
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#ifndef __OV9655_REG_REGS_H__
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#define __OV9655_REG_REGS_H__
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/* OV9655 Registers definition */
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#define OV9655_REG_GAIN 0x00
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#define OV9655_REG_BLUE 0x01
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#define OV9655_REG_RED 0x02
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#define OV9655_REG_VREF 0x03
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#define OV9655_REG_COM1 0x04
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#define OV9655_REG_BAVE 0x05
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#define OV9655_REG_GbAVE 0x06
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#define OV9655_REG_GrAVE 0x07
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#define OV9655_REG_RAVE 0x08
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#define OV9655_REG_COM2 0x09
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#define OV9655_REG_PID 0x0A
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#define OV9655_REG_VER 0x0B
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#define OV9655_REG_COM3 0x0C
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#define OV9655_REG_COM4 0x0D
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#define OV9655_REG_COM5 0x0E
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#define OV9655_REG_COM6 0x0F
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#define OV9655_REG_AEC 0x10
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#define OV9655_REG_CLKRC 0x11
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#define OV9655_REG_COM7 0x12
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#define OV9655_REG_COM8 0x13
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#define OV9655_REG_COM9 0x14
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#define OV9655_REG_COM10 0x15
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#define OV9655_REG_REG16 0x16
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#define OV9655_REG_HSTART 0x17
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#define OV9655_REG_HSTOP 0x18
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#define OV9655_REG_VSTART 0x19
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#define OV9655_REG_VSTOP 0x1A
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#define OV9655_REG_PSHFT 0x1B
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#define OV9655_REG_MIDH 0x1C
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#define OV9655_REG_MIDL 0x1D
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#define OV9655_REG_MVFP 0x1E
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#define OV9655_REG_BOS 0x20
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#define OV9655_REG_GBOS 0x21
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#define OV9655_REG_GROS 0x22
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#define OV9655_REG_ROS 0x23
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#define OV9655_REG_AEW 0x24
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#define OV9655_REG_AEB 0x25
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#define OV9655_REG_VPT 0x26
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#define OV9655_REG_BBIAS 0x27
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#define OV9655_REG_GbBIAS 0x28
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#define OV9655_REG_PREGAIN 0x29
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#define OV9655_REG_EXHCH 0x2A
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#define OV9655_REG_EXHCL 0x2B
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#define OV9655_REG_RBIAS 0x2C
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#define OV9655_REG_ADVFL 0x2D
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#define OV9655_REG_ADVFH 0x2E
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#define OV9655_REG_YAVE 0x2F
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#define OV9655_REG_HSYST 0x30
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#define OV9655_REG_HSYEN 0x31
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#define OV9655_REG_HREF 0x32
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#define OV9655_REG_CHLF 0x33
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#define OV9655_REG_AREF1 0x34
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#define OV9655_REG_AREF2 0x35
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#define OV9655_REG_AREF3 0x36
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#define OV9655_REG_ADC1 0x37
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#define OV9655_REG_ADC2 0x38
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#define OV9655_REG_AREF4 0x39
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#define OV9655_REG_TSLB 0x3A
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#define OV9655_REG_COM11 0x3B
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#define OV9655_REG_COM12 0x3C
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#define OV9655_REG_COM13 0x3D
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#define OV9655_REG_COM14 0x3E
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#define OV9655_REG_EDGE 0x3F
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#define OV9655_REG_COM15 0x40
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#define OV9655_REG_COM16 0x41
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#define OV9655_REG_COM17 0x42
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#define OV9655_REG_MTX1 0x4F
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#define OV9655_REG_MTX2 0x50
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#define OV9655_REG_MTX3 0x51
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#define OV9655_REG_MTX4 0x52
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#define OV9655_REG_MTX5 0x53
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#define OV9655_REG_MTX6 0x54
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#define OV9655_REG_BRTN 0x55
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#define OV9655_REG_CNST1 0x56
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#define OV9655_REG_CNST2 0x57
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#define OV9655_REG_MTXS 0x58
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#define OV9655_REG_AWBOP1 0x59
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#define OV9655_REG_AWBOP2 0x5A
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#define OV9655_REG_AWBOP3 0x5B
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#define OV9655_REG_AWBOP4 0x5C
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#define OV9655_REG_AWBOP5 0x5D
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#define OV9655_REG_AWBOP6 0x5E
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#define OV9655_REG_BLMT 0x5F
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#define OV9655_REG_RLMT 0x60
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#define OV9655_REG_GLMT 0x61
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#define OV9655_REG_LCC1 0x62
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#define OV9655_REG_LCC2 0x63
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#define OV9655_REG_LCC3 0x64
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#define OV9655_REG_LCC4 0x65
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#define OV9655_REG_MANU 0x66
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#define OV9655_REG_MANV 0x67
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#define OV9655_REG_MANY 0x68
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#define OV9655_REG_VARO 0x69
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#define OV9655_REG_BD50MAX 0x6A
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#define OV9655_REG_DBLV 0x6B
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#define OV9655_REG_DNSTH 0x70
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#define OV9655_REG_POIDX 0x72
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#define OV9655_REG_PCKDV 0x73
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#define OV9655_REG_XINDX 0x74
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#define OV9655_REG_YINDX 0x75
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#define OV9655_REG_SLOP 0x7A
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#define OV9655_REG_GAM1 0x7B
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#define OV9655_REG_GAM2 0x7C
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#define OV9655_REG_GAM3 0x7D
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#define OV9655_REG_GAM4 0x7E
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#define OV9655_REG_GAM5 0x7F
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#define OV9655_REG_GAM6 0x80
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#define OV9655_REG_GAM7 0x81
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#define OV9655_REG_GAM8 0x82
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#define OV9655_REG_GAM9 0x83
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#define OV9655_REG_GAM10 0x84
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#define OV9655_REG_GAM11 0x85
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#define OV9655_REG_GAM12 0x86
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#define OV9655_REG_GAM13 0x87
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#define OV9655_REG_GAM14 0x88
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#define OV9655_REG_GAM15 0x89
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#define OV9655_REG_COM18 0x8B
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#define OV9655_REG_COM19 0x8C
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#define OV9655_REG_COM20 0x8D
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#define OV9655_REG_DMLNL 0x92
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#define OV9655_REG_DMLNH 0x93
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#define OV9655_REG_LCC6 0x9D
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#define OV9655_REG_LCC7 0x9E
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#define OV9655_REG_AECH 0xA1
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#define OV9655_REG_BD50 0xA2
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#define OV9655_REG_BD60 0xA3
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#define OV9655_REG_COM21 0xA4
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#define OV9655_REG_GREEN 0xA6
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#define OV9655_REG_VZST 0xA7
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#define OV9655_REG_REFA8 0xA8
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#define OV9655_REG_REFA9 0xA9
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#define OV9655_REG_BLC1 0xAC
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#define OV9655_REG_BLC2 0xAD
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#define OV9655_REG_BLC3 0xAE
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#define OV9655_REG_BLC4 0xAF
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#define OV9655_REG_BLC5 0xB0
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#define OV9655_REG_BLC6 0xB1
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#define OV9655_REG_BLC7 0xB2
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#define OV9655_REG_BLC8 0xB3
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#define OV9655_REG_CTRLB4 0xB4
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#define OV9655_REG_FRSTL 0xB7
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#define OV9655_REG_FRSTH 0xB8
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#define OV9655_REG_ADBOFF 0xBC
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#define OV9655_REG_ADROFF 0xBD
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#define OV9655_REG_ADGbOFF 0xBE
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#define OV9655_REG_ADGrOFF 0xBF
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#define OV9655_REG_COM23 0xC4
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#define OV9655_REG_BD60MAX 0xC5
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#define OV9655_REG_COM24 0xC7
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/* Registers bit definition */
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/* COM1 Register */
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#define CCIR656_FORMAT 0x40
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#define HREF_SKIP_0 0x00
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#define HREF_SKIP_1 0x04
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#define HREF_SKIP_3 0x08
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/* COM2 Register */
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#define SOFT_SLEEP_MODE 0x10
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#define ODCAP_1x 0x00
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#define ODCAP_2x 0x01
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#define ODCAP_3x 0x02
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#define ODCAP_4x 0x03
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/* COM3 Register */
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#define COLOR_BAR_OUTPUT 0x80
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#define OUTPUT_MSB_LAS_SWAP 0x40
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#define PIN_REMAP_RESETB_EXPST 0x08
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#define RGB565_FORMAT 0x00
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#define RGB_OUTPUT_AVERAGE 0x04
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#define SINGLE_FRAME 0x01
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/* COM5 Register */
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#define SLAM_MODE_ENABLE 0x40
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#define EXPOSURE_NORMAL_MODE 0x01
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/* COM7 Register */
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#define SCCB_REG_RESET 0x80
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#define FORMAT_CTRL_15fpsVGA 0x00
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#define FORMAT_CTRL_30fpsVGA_NoVArioPixel 0x50
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#define FORMAT_CTRL_30fpsVGA_VArioPixel 0x60
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#define OUTPUT_FORMAT_RAWRGB 0x00
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#define OUTPUT_FORMAT_RAWRGB_DATA 0x00
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#define OUTPUT_FORMAT_RAWRGB_INTERP 0x01
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#define OUTPUT_FORMAT_YUV 0x02
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#define OUTPUT_FORMAT_RGB 0x03
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/* COM9 Register */
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#define GAIN_2x 0x00
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#define GAIN_4x 0x10
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#define GAIN_8x 0x20
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#define GAIN_16x 0x30
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#define GAIN_32x 0x40
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#define GAIN_64x 0x50
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#define GAIN_128x 0x60
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#define DROP_VSYNC 0x04
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#define DROP_HREF 0x02
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/* COM10 Register */
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#define RESETb_REMAP_SLHS 0x80
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#define HREF_CHANGE_HSYNC 0x40
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#define PCLK_ON 0x00
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#define PCLK_OFF 0x20
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#define PCLK_POLARITY_REV 0x10
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#define HREF_POLARITY_REV 0x08
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#define RESET_ENDPOINT 0x04
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#define VSYNC_NEG 0x02
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#define HSYNC_NEG 0x01
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/* TSLB Register */
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#define PCLK_DELAY_0 0x00
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#define PCLK_DELAY_2 0x40
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#define PCLK_DELAY_4 0x80
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#define PCLK_DELAY_6 0xC0
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#define OUTPUT_BITWISE_REV 0x20
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#define UV_NORMAL 0x00
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#define UV_FIXED 0x10
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#define YUV_SEQ_YUYV 0x00
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#define YUV_SEQ_YVYU 0x02
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#define YUV_SEQ_VYUY 0x04
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#define YUV_SEQ_UYVY 0x06
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#define BANDING_FREQ_50 0x02
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#define RGB_NORMAL 0x00
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#define RGB_565 0x10
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#define RGB_555 0x30
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#endif //__GC032A_REG_REGS_H__
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